Better PPA
Smaller, faster, lower-power blocks.
Area, frequency, and power from your synthesis and STA reports.
AI deployment for your semiconductor engineering.
We work side by side with your engineers to bring AI into the flows you already run. Your own chip tools check every result, and each round starts from what worked.
Illustrative. Many agents write RTL in parallel. Your tools check every design. Good branches merge, and every lesson is shared with the whole swarm.
Team and advisors from
Backed by
A chip model that delivers what your engineers measure.
It learns your designs, libraries, and past runs, and it improves every round. Your own tools report every result.
Bugs found earlier
More bugs caught in regression, fewer found late.
Bugs found per week, and late-stage escapes.
Faster coverage closure
Reach your coverage goals with fewer simulation cycles.
Functional and code coverage per cycle spent.
Faster timing closure
Fewer iterations from spec to timing closure.
Iterations and engineer hours per block.
Today With our chip model · Illustrative curves. In a pilot, we measure each one in your flow, against your current baseline.
Every checked run teaches the next.
Simulation, lint, synthesis, and timing reports grade every attempt. Graded runs become lessons and training data. The loop widens from one block to a workflow, then to the whole team.
Read our research →Hands-on, with your team.
We have built custom systems with an AI accelerator company and a GPU company.
Map
We walk through your workflows together and start with the one that matters most.
Build
We turn past runs and expert fixes into datasets, checks, and models your company owns.
Deploy
We build AI into the tools and scripts you already run, then expand to the next workflow.
Demo.
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DemoHill-Climbing Chip Design with a Self-Improving Loop
+42% score
Our loop beat the best frontier coding agent on all six design variants, and every design was bit-exact.
Read the write-up
DemoPost-Training a Professional Chip Coding Model
27B model · 87.8% pass rate
Our results on NVIDIA’s CVDP, the RTL failure modes that frontier models hit, and the SFT and RL pipeline we built around them.
Read the write-up
BenchmarkChipBench: Benchmarking LLM Agents for Chip Design
Our tasks span CPU, accelerator and network design.
Visit chipbench.aiYour designs stay with you.
Built to run on machines you control. The datasets, checks, and models we build belong to your company.
Frontier AI and silicon engineering, in one team.
Yiqian Min
Silicon architecture & verification
15 years in chip design. Memory subsystem architecture for Meta’s MTIA accelerator. Networking silicon at Marvell. CPU verification on Apple A5–A7.
Jiachen “Amber” Liu
AI & training
AI Researcher at Meta. Ph.D. in Machine Learning Systems, University of Michigan. ML research at MIT and Apple.